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<ul>
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
<li><a href="#resource" style=" font-size: 16px;">Resource</a>
<ul>
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
</ul>
</li>
<li><a href="#timing" style=" font-size: 16px;">Timing</a>
<ul>
<li><a href="#clock" style=" font-size: 14px;">Clock Summary</a></li>
<li><a href="#performance" style=" font-size: 14px;">Max Frequency Summary</a></li>
<li><a href="#detail timing" style=" font-size: 14px;">Detail Timing Paths Informations</a></li>
</ul>
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<div id="content">
<h1><a name="about">Synthesis Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>GowinSynthesis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>D:\gowin_crush\gowin_proj_audio_PT8211\fpga_project\src\RTL\USB_CORE\fpga_top_usb_serial.v<br>
D:\gowin_crush\gowin_proj_audio_PT8211\fpga_project\src\RTL\USB_CORE\usb_audio_top.v<br>
D:\gowin_crush\gowin_proj_audio_PT8211\fpga_project\src\RTL\USB_CORE\usb_serial_top.v<br>
D:\gowin_crush\gowin_proj_audio_PT8211\fpga_project\src\RTL\USB_CORE\usbfs_bitlevel.v<br>
D:\gowin_crush\gowin_proj_audio_PT8211\fpga_project\src\RTL\USB_CORE\usbfs_core_top.v<br>
D:\gowin_crush\gowin_proj_audio_PT8211\fpga_project\src\RTL\USB_CORE\usbfs_debug_monitor.v<br>
D:\gowin_crush\gowin_proj_audio_PT8211\fpga_project\src\RTL\USB_CORE\usbfs_debug_uart_tx.v<br>
D:\gowin_crush\gowin_proj_audio_PT8211\fpga_project\src\RTL\USB_CORE\usbfs_packet_rx.v<br>
D:\gowin_crush\gowin_proj_audio_PT8211\fpga_project\src\RTL\USB_CORE\usbfs_packet_tx.v<br>
D:\gowin_crush\gowin_proj_audio_PT8211\fpga_project\src\RTL\USB_CORE\usbfs_transaction.v<br>
D:\gowin_crush\gowin_proj_audio_PT8211\fpga_project\src\RTL\async_fifo.v<br>
D:\gowin_crush\gowin_proj_audio_PT8211\fpga_project\src\RTL\clock_tree.v<br>
D:\gowin_crush\gowin_proj_audio_PT8211\fpga_project\src\RTL\key_debounce.v<br>
D:\gowin_crush\gowin_proj_audio_PT8211\fpga_project\src\RTL\led_driver.v<br>
D:\gowin_crush\gowin_proj_audio_PT8211\fpga_project\src\RTL\LSBJ_audio_driver.v<br>
D:\gowin_crush\gowin_proj_audio_PT8211\fpga_project\src\RTL\volume_control.v<br>
D:\gowin_crush\gowin_proj_audio_PT8211\fpga_project\src\IP_CORE\audio_master_rpll\audio_master.v<br>
D:\gowin_crush\gowin_proj_audio_PT8211\fpga_project\src\IP_CORE\audio_rpll\audio_rpll.v<br>
D:\gowin_crush\gowin_proj_audio_PT8211\fpga_project\src\IP_CORE\usb_rpll\usb_rpll.v<br>
D:\gowin_crush\gowin_proj_audio_PT8211\fpga_project\src\RTL\lckfb_usb_audio.v<br>
</td>
</tr>
<tr>
<td class="label">GowinSynthesis Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Tool Version</td>
<td>V1.9.10.03 (64-bit)</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW2A-LV18PG256C8/I7</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW2A-18</td>
</tr>
<tr>
<td class="label">Device Version</td>
<td>C</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Sat Apr 19 12:55:13 2025
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.</td>
</tr>
</table>
<h1><a name="summary">Synthesis Details</a></h1>
<table class="summary_table">
<tr>
<td class="label">Top Level Module</td>
<td>lckfb_usb_audio</td>
</tr>
<tr>
<td class="label">Synthesis Process</td>
<td>Running parser:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.265s, Peak memory usage = 526.441MB<br/>Running netlist conversion:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.076s, Peak memory usage = 526.441MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.033s, Peak memory usage = 526.441MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.069s, Peak memory usage = 526.441MB<br/>Running inference:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.031s, Peak memory usage = 526.441MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 526.441MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 526.441MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 526.441MB<br/>Running technical mapping:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.097s, Peak memory usage = 526.441MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 526.441MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 526.441MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 3: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 526.441MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 4: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.11s, Peak memory usage = 526.441MB<br/>Generate output files:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.105s, Peak memory usage = 526.441MB<br/></td>
</tr>
<tr>
<td class="label">Total Time and Memory Usage</td>
<td>CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 526.441MB</td>
</tr>
</table>
<h1><a name="resource">Resource</a></h1>
<h2><a name="usage">Resource Usage Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
</tr>
<tr>
<td class="label"><b>I/O Port </b></td>
<td>22</td>
</tr>
<tr>
<td class="label"><b>I/O Buf </b></td>
<td>22</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspIBUF</td>
<td>3</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspOBUF</td>
<td>17</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspIOBUF</td>
<td>2</td>
</tr>
<tr>
<td class="label"><b>Register </b></td>
<td>625</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFF</td>
<td>8</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFS</td>
<td>8</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFSE</td>
<td>18</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFR</td>
<td>77</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFRE</td>
<td>116</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFP</td>
<td>1</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFPE</td>
<td>38</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFC</td>
<td>81</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFCE</td>
<td>278</td>
</tr>
<tr>
<td class="label"><b>LUT </b></td>
<td>1136</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT2</td>
<td>147</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT3</td>
<td>298</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT4</td>
<td>691</td>
</tr>
<tr>
<td class="label"><b>ALU </b></td>
<td>277</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspALU</td>
<td>277</td>
</tr>
<tr>
<td class="label"><b>INV </b></td>
<td>20</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspINV</td>
<td>20</td>
</tr>
<tr>
<td class="label"><b>BSRAM </b></td>
<td>2</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspSDPB</td>
<td>2</td>
</tr>
<tr>
<td class="label"><b>CLOCK </b></td>
<td>3</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbsprPLL</td>
<td>3</td>
</tr>
</table>
<h2><a name="utilization">Resource Utilization Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
<td><b>Utilization</b></td>
</tr>
<tr>
<td class="label">Logic</td>
<td>1433(1156 LUT, 277 ALU) / 20736</td>
<td>7%</td>
</tr>
<tr>
<td class="label">Register</td>
<td>625 / 16173</td>
<td>4%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as Latch</td>
<td>0 / 16173</td>
<td>0%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as FF</td>
<td>625 / 16173</td>
<td>4%</td>
</tr>
<tr>
<td class="label">BSRAM</td>
<td>2 / 46</td>
<td>5%</td>
</tr>
</table>
<h1><a name="timing">Timing</a></h1>
<h2><a name="clock">Clock Summary:</a></h2>
<table class="summary_table">
<tr>
<th>NO.</th>
<th>Clock Name</th>
<th>Type</th>
<th>Period</th>
<th>Frequency(MHz)</th>
<th>Rise</th>
<th>Fall</th>
<th>Source</th>
<th>Master</th>
<th>Object</th>
</tr>
<tr>
<td>1</td>
<td>clk50mhz</td>
<td>Base</td>
<td>20.000</td>
<td>50.0</td>
<td>0.000</td>
<td>10.000</td>
<td> </td>
<td> </td>
<td>clk50mhz_ibuf/I </td>
</tr>
<tr>
<td>2</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Generated</td>
<td>16.667</td>
<td>60.0</td>
<td>0.000</td>
<td>8.333</td>
<td>clk50mhz_ibuf/I</td>
<td>clk50mhz</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT </td>
</tr>
<tr>
<td>3</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Generated</td>
<td>16.667</td>
<td>60.0</td>
<td>0.000</td>
<td>8.333</td>
<td>clk50mhz_ibuf/I</td>
<td>clk50mhz</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUTP </td>
</tr>
<tr>
<td>4</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Generated</td>
<td>33.333</td>
<td>30.0</td>
<td>0.000</td>
<td>16.667</td>
<td>clk50mhz_ibuf/I</td>
<td>clk50mhz</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUTD </td>
</tr>
<tr>
<td>5</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Generated</td>
<td>50.000</td>
<td>20.0</td>
<td>0.000</td>
<td>25.000</td>
<td>clk50mhz_ibuf/I</td>
<td>clk50mhz</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUTD3 </td>
</tr>
<tr>
<td>6</td>
<td>u_clock_tree/your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Generated</td>
<td>13.889</td>
<td>72.0</td>
<td>0.000</td>
<td>6.944</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT.default_gen_clk</td>
<td>u_clock_tree/your_instance_name/rpll_inst/CLKOUT </td>
</tr>
<tr>
<td>7</td>
<td>u_clock_tree/your_instance_name/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Generated</td>
<td>13.889</td>
<td>72.0</td>
<td>0.000</td>
<td>6.944</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT.default_gen_clk</td>
<td>u_clock_tree/your_instance_name/rpll_inst/CLKOUTP </td>
</tr>
<tr>
<td>8</td>
<td>u_clock_tree/your_instance_name/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Generated</td>
<td>27.778</td>
<td>36.0</td>
<td>0.000</td>
<td>13.889</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT.default_gen_clk</td>
<td>u_clock_tree/your_instance_name/rpll_inst/CLKOUTD </td>
</tr>
<tr>
<td>9</td>
<td>u_clock_tree/your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Generated</td>
<td>41.667</td>
<td>24.0</td>
<td>0.000</td>
<td>20.833</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT.default_gen_clk</td>
<td>u_clock_tree/your_instance_name/rpll_inst/CLKOUTD3 </td>
</tr>
<tr>
<td>10</td>
<td>u_clock_tree/aud_pll/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Generated</td>
<td>6.510</td>
<td>153.6</td>
<td>0.000</td>
<td>3.255</td>
<td>u_clock_tree/your_instance_name/rpll_inst/CLKOUT</td>
<td>u_clock_tree/your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
<td>u_clock_tree/aud_pll/rpll_inst/CLKOUT </td>
</tr>
<tr>
<td>11</td>
<td>u_clock_tree/aud_pll/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Generated</td>
<td>6.510</td>
<td>153.6</td>
<td>0.000</td>
<td>3.255</td>
<td>u_clock_tree/your_instance_name/rpll_inst/CLKOUT</td>
<td>u_clock_tree/your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
<td>u_clock_tree/aud_pll/rpll_inst/CLKOUTP </td>
</tr>
<tr>
<td>12</td>
<td>u_clock_tree/aud_pll/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Generated</td>
<td>325.521</td>
<td>3.1</td>
<td>0.000</td>
<td>162.760</td>
<td>u_clock_tree/your_instance_name/rpll_inst/CLKOUT</td>
<td>u_clock_tree/your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
<td>u_clock_tree/aud_pll/rpll_inst/CLKOUTD </td>
</tr>
<tr>
<td>13</td>
<td>u_clock_tree/aud_pll/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Generated</td>
<td>19.531</td>
<td>51.2</td>
<td>0.000</td>
<td>9.766</td>
<td>u_clock_tree/your_instance_name/rpll_inst/CLKOUT</td>
<td>u_clock_tree/your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
<td>u_clock_tree/aud_pll/rpll_inst/CLKOUTD3 </td>
</tr>
</table>
<h2><a name="performance">Max Frequency Summary:</a></h2>
<table class="summary_table">
<tr>
<th>NO.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT.default_gen_clk</td>
<td>60.000(MHz)</td>
<td>135.450(MHz)</td>
<td>8</td>
<td>TOP</td>
</tr>
<tr>
<td>2</td>
<td>u_clock_tree/aud_pll/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>3.072(MHz)</td>
<td>115.652(MHz)</td>
<td>10</td>
<td>TOP</td>
</tr>
</table>
<h2><a name="detail timing">Detail Timing Paths Information</a></h2>
<h3>Path&nbsp1</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>9.284</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.208</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.491</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_audio_fifo/rd_counter_green_sync1_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_audio_fifo/wr_counter_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT.default_gen_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT.default_gen_clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.500</td>
<td>0.500</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>0.860</td>
<td>0.360</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_audio_fifo/rd_counter_green_sync1_3_s0/CLK</td>
</tr>
<tr>
<td>1.092</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>4</td>
<td>u_audio_fifo/rd_counter_green_sync1_3_s0/Q</td>
</tr>
<tr>
<td>1.566</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_audio_fifo/rd_counter_bin_2_s1/I1</td>
</tr>
<tr>
<td>2.121</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>u_audio_fifo/rd_counter_bin_2_s1/F</td>
</tr>
<tr>
<td>2.595</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_audio_fifo/rd_counter_bin_1_s0/I1</td>
</tr>
<tr>
<td>3.150</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>u_audio_fifo/rd_counter_bin_1_s0/F</td>
</tr>
<tr>
<td>3.624</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_audio_fifo/rd_counter_bin_0_s0/I1</td>
</tr>
<tr>
<td>4.179</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>u_audio_fifo/rd_counter_bin_0_s0/F</td>
</tr>
<tr>
<td>4.653</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>u_audio_fifo/n322_s/I0</td>
</tr>
<tr>
<td>5.202</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>u_audio_fifo/n322_s/COUT</td>
</tr>
<tr>
<td>5.202</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>u_audio_fifo/n321_s/CIN</td>
</tr>
<tr>
<td>5.237</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>u_audio_fifo/n321_s/COUT</td>
</tr>
<tr>
<td>5.237</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>u_audio_fifo/n320_s/CIN</td>
</tr>
<tr>
<td>5.272</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>u_audio_fifo/n320_s/COUT</td>
</tr>
<tr>
<td>5.272</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>u_audio_fifo/n319_s/CIN</td>
</tr>
<tr>
<td>5.307</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>u_audio_fifo/n319_s/COUT</td>
</tr>
<tr>
<td>5.307</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>u_audio_fifo/n318_s/CIN</td>
</tr>
<tr>
<td>5.343</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>u_audio_fifo/n318_s/COUT</td>
</tr>
<tr>
<td>5.343</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>u_audio_fifo/n317_s/CIN</td>
</tr>
<tr>
<td>5.813</td>
<td>0.470</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>u_audio_fifo/n317_s/SUM</td>
</tr>
<tr>
<td>6.287</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_audio_fifo/n6_s1/I0</td>
</tr>
<tr>
<td>6.804</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>u_audio_fifo/n6_s1/F</td>
</tr>
<tr>
<td>7.278</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_audio_fifo/n6_s4/I1</td>
</tr>
<tr>
<td>7.848</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>5</td>
<td>u_audio_fifo/n6_s4/F</td>
</tr>
<tr>
<td>8.208</td>
<td>0.360</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_audio_fifo/wr_counter_5_s0/CE</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>17.166</td>
<td>0.500</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>17.526</td>
<td>0.360</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_audio_fifo/wr_counter_5_s0/CLK</td>
</tr>
<tr>
<td>17.491</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>u_audio_fifo/wr_counter_5_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.360, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 3.912, 53.238%; route: 3.204, 43.605%; tC2Q: 0.232, 3.157%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.360, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp2</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>9.284</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.208</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.491</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_audio_fifo/rd_counter_green_sync1_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_audio_fifo/wr_counter_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT.default_gen_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT.default_gen_clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.500</td>
<td>0.500</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>0.860</td>
<td>0.360</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_audio_fifo/rd_counter_green_sync1_3_s0/CLK</td>
</tr>
<tr>
<td>1.092</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>4</td>
<td>u_audio_fifo/rd_counter_green_sync1_3_s0/Q</td>
</tr>
<tr>
<td>1.566</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_audio_fifo/rd_counter_bin_2_s1/I1</td>
</tr>
<tr>
<td>2.121</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>u_audio_fifo/rd_counter_bin_2_s1/F</td>
</tr>
<tr>
<td>2.595</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_audio_fifo/rd_counter_bin_1_s0/I1</td>
</tr>
<tr>
<td>3.150</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>u_audio_fifo/rd_counter_bin_1_s0/F</td>
</tr>
<tr>
<td>3.624</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_audio_fifo/rd_counter_bin_0_s0/I1</td>
</tr>
<tr>
<td>4.179</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>u_audio_fifo/rd_counter_bin_0_s0/F</td>
</tr>
<tr>
<td>4.653</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>u_audio_fifo/n322_s/I0</td>
</tr>
<tr>
<td>5.202</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>u_audio_fifo/n322_s/COUT</td>
</tr>
<tr>
<td>5.202</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>u_audio_fifo/n321_s/CIN</td>
</tr>
<tr>
<td>5.237</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>u_audio_fifo/n321_s/COUT</td>
</tr>
<tr>
<td>5.237</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>u_audio_fifo/n320_s/CIN</td>
</tr>
<tr>
<td>5.272</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>u_audio_fifo/n320_s/COUT</td>
</tr>
<tr>
<td>5.272</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>u_audio_fifo/n319_s/CIN</td>
</tr>
<tr>
<td>5.307</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>u_audio_fifo/n319_s/COUT</td>
</tr>
<tr>
<td>5.307</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>u_audio_fifo/n318_s/CIN</td>
</tr>
<tr>
<td>5.343</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>u_audio_fifo/n318_s/COUT</td>
</tr>
<tr>
<td>5.343</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>u_audio_fifo/n317_s/CIN</td>
</tr>
<tr>
<td>5.813</td>
<td>0.470</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>u_audio_fifo/n317_s/SUM</td>
</tr>
<tr>
<td>6.287</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_audio_fifo/n6_s1/I0</td>
</tr>
<tr>
<td>6.804</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>u_audio_fifo/n6_s1/F</td>
</tr>
<tr>
<td>7.278</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_audio_fifo/n6_s4/I1</td>
</tr>
<tr>
<td>7.848</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>5</td>
<td>u_audio_fifo/n6_s4/F</td>
</tr>
<tr>
<td>8.208</td>
<td>0.360</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_audio_fifo/wr_counter_1_s0/CE</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>17.166</td>
<td>0.500</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>17.526</td>
<td>0.360</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_audio_fifo/wr_counter_1_s0/CLK</td>
</tr>
<tr>
<td>17.491</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>u_audio_fifo/wr_counter_1_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.360, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 3.912, 53.238%; route: 3.204, 43.605%; tC2Q: 0.232, 3.157%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.360, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp3</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>9.284</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.208</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.491</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_audio_fifo/rd_counter_green_sync1_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_audio_fifo/wr_counter_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT.default_gen_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT.default_gen_clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.500</td>
<td>0.500</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>0.860</td>
<td>0.360</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_audio_fifo/rd_counter_green_sync1_3_s0/CLK</td>
</tr>
<tr>
<td>1.092</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>4</td>
<td>u_audio_fifo/rd_counter_green_sync1_3_s0/Q</td>
</tr>
<tr>
<td>1.566</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_audio_fifo/rd_counter_bin_2_s1/I1</td>
</tr>
<tr>
<td>2.121</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>u_audio_fifo/rd_counter_bin_2_s1/F</td>
</tr>
<tr>
<td>2.595</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_audio_fifo/rd_counter_bin_1_s0/I1</td>
</tr>
<tr>
<td>3.150</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>u_audio_fifo/rd_counter_bin_1_s0/F</td>
</tr>
<tr>
<td>3.624</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_audio_fifo/rd_counter_bin_0_s0/I1</td>
</tr>
<tr>
<td>4.179</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>u_audio_fifo/rd_counter_bin_0_s0/F</td>
</tr>
<tr>
<td>4.653</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>u_audio_fifo/n322_s/I0</td>
</tr>
<tr>
<td>5.202</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>u_audio_fifo/n322_s/COUT</td>
</tr>
<tr>
<td>5.202</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>u_audio_fifo/n321_s/CIN</td>
</tr>
<tr>
<td>5.237</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>u_audio_fifo/n321_s/COUT</td>
</tr>
<tr>
<td>5.237</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>u_audio_fifo/n320_s/CIN</td>
</tr>
<tr>
<td>5.272</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>u_audio_fifo/n320_s/COUT</td>
</tr>
<tr>
<td>5.272</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>u_audio_fifo/n319_s/CIN</td>
</tr>
<tr>
<td>5.307</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>u_audio_fifo/n319_s/COUT</td>
</tr>
<tr>
<td>5.307</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>u_audio_fifo/n318_s/CIN</td>
</tr>
<tr>
<td>5.343</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>u_audio_fifo/n318_s/COUT</td>
</tr>
<tr>
<td>5.343</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>u_audio_fifo/n317_s/CIN</td>
</tr>
<tr>
<td>5.813</td>
<td>0.470</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>u_audio_fifo/n317_s/SUM</td>
</tr>
<tr>
<td>6.287</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_audio_fifo/n6_s1/I0</td>
</tr>
<tr>
<td>6.804</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>u_audio_fifo/n6_s1/F</td>
</tr>
<tr>
<td>7.278</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_audio_fifo/n6_s4/I1</td>
</tr>
<tr>
<td>7.848</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>5</td>
<td>u_audio_fifo/n6_s4/F</td>
</tr>
<tr>
<td>8.208</td>
<td>0.360</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_audio_fifo/wr_counter_2_s0/CE</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>17.166</td>
<td>0.500</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>17.526</td>
<td>0.360</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_audio_fifo/wr_counter_2_s0/CLK</td>
</tr>
<tr>
<td>17.491</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>u_audio_fifo/wr_counter_2_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.360, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 3.912, 53.238%; route: 3.204, 43.605%; tC2Q: 0.232, 3.157%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.360, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp4</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>9.284</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.208</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.491</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_audio_fifo/rd_counter_green_sync1_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_audio_fifo/wr_counter_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT.default_gen_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT.default_gen_clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.500</td>
<td>0.500</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>0.860</td>
<td>0.360</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_audio_fifo/rd_counter_green_sync1_3_s0/CLK</td>
</tr>
<tr>
<td>1.092</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>4</td>
<td>u_audio_fifo/rd_counter_green_sync1_3_s0/Q</td>
</tr>
<tr>
<td>1.566</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_audio_fifo/rd_counter_bin_2_s1/I1</td>
</tr>
<tr>
<td>2.121</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>u_audio_fifo/rd_counter_bin_2_s1/F</td>
</tr>
<tr>
<td>2.595</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_audio_fifo/rd_counter_bin_1_s0/I1</td>
</tr>
<tr>
<td>3.150</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>u_audio_fifo/rd_counter_bin_1_s0/F</td>
</tr>
<tr>
<td>3.624</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_audio_fifo/rd_counter_bin_0_s0/I1</td>
</tr>
<tr>
<td>4.179</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>u_audio_fifo/rd_counter_bin_0_s0/F</td>
</tr>
<tr>
<td>4.653</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>u_audio_fifo/n322_s/I0</td>
</tr>
<tr>
<td>5.202</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>u_audio_fifo/n322_s/COUT</td>
</tr>
<tr>
<td>5.202</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>u_audio_fifo/n321_s/CIN</td>
</tr>
<tr>
<td>5.237</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>u_audio_fifo/n321_s/COUT</td>
</tr>
<tr>
<td>5.237</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>u_audio_fifo/n320_s/CIN</td>
</tr>
<tr>
<td>5.272</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>u_audio_fifo/n320_s/COUT</td>
</tr>
<tr>
<td>5.272</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>u_audio_fifo/n319_s/CIN</td>
</tr>
<tr>
<td>5.307</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>u_audio_fifo/n319_s/COUT</td>
</tr>
<tr>
<td>5.307</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>u_audio_fifo/n318_s/CIN</td>
</tr>
<tr>
<td>5.343</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>u_audio_fifo/n318_s/COUT</td>
</tr>
<tr>
<td>5.343</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>u_audio_fifo/n317_s/CIN</td>
</tr>
<tr>
<td>5.813</td>
<td>0.470</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>u_audio_fifo/n317_s/SUM</td>
</tr>
<tr>
<td>6.287</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_audio_fifo/n6_s1/I0</td>
</tr>
<tr>
<td>6.804</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>u_audio_fifo/n6_s1/F</td>
</tr>
<tr>
<td>7.278</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_audio_fifo/n6_s4/I1</td>
</tr>
<tr>
<td>7.848</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>5</td>
<td>u_audio_fifo/n6_s4/F</td>
</tr>
<tr>
<td>8.208</td>
<td>0.360</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_audio_fifo/wr_counter_3_s0/CE</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>17.166</td>
<td>0.500</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>17.526</td>
<td>0.360</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_audio_fifo/wr_counter_3_s0/CLK</td>
</tr>
<tr>
<td>17.491</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>u_audio_fifo/wr_counter_3_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.360, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 3.912, 53.238%; route: 3.204, 43.605%; tC2Q: 0.232, 3.157%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.360, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp5</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>9.284</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.208</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.491</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_audio_fifo/rd_counter_green_sync1_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_audio_fifo/wr_counter_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT.default_gen_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT.default_gen_clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.500</td>
<td>0.500</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>0.860</td>
<td>0.360</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_audio_fifo/rd_counter_green_sync1_3_s0/CLK</td>
</tr>
<tr>
<td>1.092</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>4</td>
<td>u_audio_fifo/rd_counter_green_sync1_3_s0/Q</td>
</tr>
<tr>
<td>1.566</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_audio_fifo/rd_counter_bin_2_s1/I1</td>
</tr>
<tr>
<td>2.121</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>u_audio_fifo/rd_counter_bin_2_s1/F</td>
</tr>
<tr>
<td>2.595</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_audio_fifo/rd_counter_bin_1_s0/I1</td>
</tr>
<tr>
<td>3.150</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>u_audio_fifo/rd_counter_bin_1_s0/F</td>
</tr>
<tr>
<td>3.624</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_audio_fifo/rd_counter_bin_0_s0/I1</td>
</tr>
<tr>
<td>4.179</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>u_audio_fifo/rd_counter_bin_0_s0/F</td>
</tr>
<tr>
<td>4.653</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>u_audio_fifo/n322_s/I0</td>
</tr>
<tr>
<td>5.202</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>u_audio_fifo/n322_s/COUT</td>
</tr>
<tr>
<td>5.202</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>u_audio_fifo/n321_s/CIN</td>
</tr>
<tr>
<td>5.237</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>u_audio_fifo/n321_s/COUT</td>
</tr>
<tr>
<td>5.237</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>u_audio_fifo/n320_s/CIN</td>
</tr>
<tr>
<td>5.272</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>u_audio_fifo/n320_s/COUT</td>
</tr>
<tr>
<td>5.272</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>u_audio_fifo/n319_s/CIN</td>
</tr>
<tr>
<td>5.307</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>u_audio_fifo/n319_s/COUT</td>
</tr>
<tr>
<td>5.307</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>u_audio_fifo/n318_s/CIN</td>
</tr>
<tr>
<td>5.343</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>u_audio_fifo/n318_s/COUT</td>
</tr>
<tr>
<td>5.343</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>u_audio_fifo/n317_s/CIN</td>
</tr>
<tr>
<td>5.813</td>
<td>0.470</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>u_audio_fifo/n317_s/SUM</td>
</tr>
<tr>
<td>6.287</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_audio_fifo/n6_s1/I0</td>
</tr>
<tr>
<td>6.804</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>u_audio_fifo/n6_s1/F</td>
</tr>
<tr>
<td>7.278</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_audio_fifo/n6_s4/I1</td>
</tr>
<tr>
<td>7.848</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>5</td>
<td>u_audio_fifo/n6_s4/F</td>
</tr>
<tr>
<td>8.208</td>
<td>0.360</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_audio_fifo/wr_counter_4_s0/CE</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>17.166</td>
<td>0.500</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>17.526</td>
<td>0.360</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_audio_fifo/wr_counter_4_s0/CLK</td>
</tr>
<tr>
<td>17.491</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>u_audio_fifo/wr_counter_4_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.360, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 3.912, 53.238%; route: 3.204, 43.605%; tC2Q: 0.232, 3.157%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.360, 100.000%</td></tr>
</table>
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